In certain circuit applications, a power Field Effect Transistor (FET) switch is needed that can withstand a very high voltage between its drain and source terminals. The high voltage may be a voltage higher than any available power FET can withstand. Several different stacked circuits are known in which multiple power FETs are connected in a “stacked” or “chained” fashion. The drain of a power FET of the stack is coupled to the source of the power FET next higher in the stack. If all the power FETs of the stack are off, then a high voltage present across the entire stack may be shared more or less equally by the various power FETs. Due to this voltage divider effect, each power FET sees a lower VDS voltage between its drain and source terminals. During switching of the overall circuit, if all the power FETs of the stack are turned on at the same time, then no one of the power FETs during turn on of the overall circuit will experience a VDS drain-to-source voltage higher than its drain-to-source breakdown voltage (BVDS). Likewise, during switching of the overall circuit, if all the power FETs are turned off at the same time, then no one of the power FETs during turn off of the overall circuit will experience a drain-to-source voltage higher than its drain-to-source BVDS breakdown voltage.